The present invention relates to an internal supply voltage generation circuit for use in semiconductor memory devices, and more particularly to an internal supply voltage generation circuit capable of readily adjusting a burn-in voltage level.
As the cell density in semiconductor memory devices increases, the corresponding size of transistor in each cell must be decreased accordingly. These increasingly small transistors experience significant stress under electric fields induced by high external voltage supplies. Thus, 16 Mbit or greater semiconductor memory devices typically provide an internal supply voltage generation circuit which supplies a voltage at lower levels than external voltage supplies. For example, a typical 16Mbit semiconductor memory device may replace an externally generated 5V supply voltage with a 4V internal supply voltage. Such reductions between external and internal operating voltages become even more pronounced in semiconductor memory devices above 16 Mbits. Thus, high density semiconductor memory devices increasingly require an internal supply voltage generation circuit which can generate a stable internal supply voltage.
FIG. 1 illustrates a conventional internal supply voltage generation circuit disclosed in article entitled "An Experimental 16-Mbit DRAM with Reduced peak-Current Noise" which appeared in the IEEE Journal of Solid-State Circuits, Vol. 24, No. 5, October 1989. The conventional internal supply voltage generation circuit includes a reference voltage generation circuit 10 for generating a reference voltage Vref, a current mirror type differential amplifier comparator 20, an output circuit 30 responsive to the output of comparator 20, an internal supply voltage generator 50 for converting the external supply voltage (ext-V.sub.cc) into an internal supply voltage (int. V.sub.cc) in response to the output of the output circuit 30. Additionally, a burn-in voltage control circuit 40 is provided for placing the semiconductor memory device in a burn-in mode, wherein high voltage, such as external supply voltage (ext.V.sub.cc), is applied to the core circuit to check long term performance of the semiconductor memory device under conditions of high voltage and high temperature.
In operation, the conventional internal supply voltage generation circuit shown in FIG. 1 applies the internal supply voltage (int. V.sub.cc) to the core circuit of the semiconductor memory device at node N4. If during operation, int. V.sub.cc drops due to current consumption in the core circuit, a comparator circuit 50A detects the drop and accordingly lowers the voltage level applied to node N3, such that pull-up transistor 19 is sharply "turned-on" to compensate for the drop in int. V.sub.cc. The foregoing circuit begins operation upon "power-on" of the semiconductor memory device, and, as shown in FIG. 2, continuously generates int. V.sub.cc after ext.V.sub.cc reaches a predetermined level.
The burn-in voltage level of the conventional circuit shown in FIG. 1 is determined by the burn-in voltage control circuit 40, and in particular by the number of diode-connected PMOS transistors 11, 12, and 13 connected in series between ext.V.sub.cc and node N2. When the need arises to change the burn-in voltage, the number of diode-connected PMOS transistors can typically be increased only by removing a metal line "I" connecting node N1 and node N2. This is accomplished by changing the mask pattern for the semiconductor memory device during manufacturing. In the particular example illustrated in FIG. 1, once metal line I has been removed, the burn-in voltage at N2 becomes (ext.V.sub.cc -3 V.sub.tp ), where V.sub.tp is the threshold voltage of each diode-connected PMOS transistor.
The conventional technique of removing metal line I by changing the mask pattern complicates production processing for the semiconductor memory device and increases production costs. These disadvantages become particularly acute for high density semiconductor memory devices having internal supply voltage generation circuits which are required to generate burn-in voltages at various levels.